上海

事大学试卷

2010 — 2011学年第二学期期末考试

:字逻辑(digital logic)》(A 卷)

班级 学号 姓名 总分

一、填空题（每空1分，共15分）请将正确答案写在题目中的括号内。

1、The period（周期）of the waveform below is ，and its frequency（频率）is

V

Z < I11K)

2、 (1110)B= D ; (27) Q= B; 156= 8421 BCD;

3、 The output of sequential logic circuit not only depends on the current inputs but also

depends on the .

4、 A 3-variable Karnaugh map has cells.

5、 A 3-bit binary counter has a maximum modulus(模)of ，A modulus-20 counter

must have at least flip-flops. A modulus-10 ring counter(环形计数器)requires

flip-flops.

6、 The frequency of the waveform at ① is and at ② is ，and the overall

modulus is •

1①I 1②

1 OO kHz ► DIV IO |~ 叫 DIV IO | ►

7、 An input variable combination that can not occur (or not allowed) can be treated as

8、 A device consists of arrangements of flip-flops which can be used to store and shift data

calls a •

二、选择题(每题1分，共计10分)

1、 The term bit means( )

(A) A small amount of data (B) a 1 or a 0 (C) binary digit (D) both answers (B) and (C)

2、 All Boolean expression can be implemented with ( )

(A) NAND gates only (B) NOR gates only

(C) combinations of AND gates，OR gates，and inverters (D) any of these

3、The modulus of a Johnson counter(扭环型计数器)with n flip-flops is ( (A)n (B)2n (C) 2°_1 (D)2n_2n

4、A 4-bit parallel adder can add ( (A) four bits in sequence (C) two 4-bit binary numbers

5、An asynchronous(异步)counter differs from a synchronous(同步)counter in ( )

(A) the number of states in its sequence (B) the method of clocking

(C) the type of flip-flops used

6、The circuit without invalid state is (

(A) the S-R latch

(C)the edge-triggered S-R flip-flop (D)the edge-triggered D flip-flop

(A) 5 (B) 6 (C)7 (D) 8

8、 The code that has an odd-parity (奇校验码)error is ( )

(A) 100110010 (B) 011101010 (C) 101111011

9、 设寄存器A,B均为四个二进制位，则A的高位清0,可由操作( )实现。

(A) AvOlll^A ； (B) AaOI U^A； (C) Av 1000^A； (D) AB^A ； (E) AaIOOO^A

10、A1，A2，A3，A4, A5是五个开关，它们闭合吋为逻辑1,断开吋为逻辑0。电灯F=1时表 示灯亮，F=0时表示灯灭。若在五个不同的地方控制同一个电灯的灭亮，逻辑函数F的表 达式是F=( )。

A- A1A2A3A4A5 B- A1+A2+A3+A4+A5 C. A1 ㊉A2㊉A3㊉A4㊉A5

三、应用题(共7题，共计53分》

1、Show the output waveform x in proper relation to the inputs with a timing diagram.(7 point)

2、Use a Karnaugh map to reduce the logic expression to a minimum SOP form(最简与或式) (8 point) • _

X = ABC + /\BC + A8(T

3、A certain application requires that a 4-bit number (A| A2 A3 A4) be decoded. Use two 74LS138 decoders to implement the logic. (8 point)

4. Write the output expression (逻辑衷达式)for the circuit below，and then develop the truth table(真值表)of this circuit (8 point )

5、For a positive edge-triggered J-K flip-flop with the inputs below, develop the Q output waveform relative to the clock (CLK)，assume that Q is initially LOW. (7 point)

6、Implement a truncated modulus-12 counter using synchronous clear input of the 74HC163

(用同步清零法实现)(The 74HC163 is 4-bit synchronous binary counter with a synchronous clear and synchronous preset input) (7 point)

7、Determine the sequence of the counter below，draw the state diagram(状态迁移图).Start with the state 000 (QoQ Q ) (8point)

四、设计题(共22分)

1 • (10 分)Design a counter to produce the following binary sequence. Use J-K flip-flops.

0,1,2,3,4,5,0,...

2、( 12 分)Use the Karnaugh map method to implement the minimum SOP expression for the logic function specified in the truth table below.

1) simplification

2) Implement the logic circuits using only NAND gates.

3) Use the 74LS151 8-input data selector to implement the circuit.

Enable

So

5,

(7)

(II)

(10)

(9)

%

d2

"4

A

(4)

(3)

(2)

(I)

(15)

(U)

(13)

MUX

EN

0A

2j

0

2

3

4

5

6 7

上海海事大学数字逻辑试卷 doc